US Patent 11929419 Semiconductor device

A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.