Patent attributes
Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.
