US Patent 11935575 Heterogeneous memory system

An example apparatus having a heterogenous memory system includes a first sensor layer, of a plurality of stacked sensor layers, including an array of pixels; and one or more semiconductor layers of the plurality of stacked sensor layers located beneath the first sensor layer, the one or more semiconductor layers configured to process pixel data output by the array of pixels, the one or more semiconductor layers including a first memory to store most significant bits (“MSBs”) of data involved in the processing of the pixel data; a second memory to store least significant bits (“LSBs”) of the data; and wherein the first memory has a lower bit error rate (“BER”) than the second memory.