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US Patent 11935593 Dummy cell resistance tuning in NAND strings

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
May 25, 2022
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Date of Patent
March 19, 2024
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Patent Application Number
17824143
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Patent Citations
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US Patent 9373396 Side wall bit line structures
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US Patent 9443597 Controlling dummy word line bias during erase in non-volatile memory
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US Patent 9449708 Nonvolatile semiconductor memory device
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US Patent 9455301 Setting channel voltages of adjustable resistance bit line structures using dummy word lines
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US Patent 9484092 Intrinsic vertical bit line architecture
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US Patent 9484093 Controlling adjustable resistance bit lines connected to word line combs
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US Patent 9922709 Memory hole bit line structures
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US Patent 10373697 Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors
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US Patent 10008271 Programming of dummy memory cell to reduce charge loss in select gate transistor
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US Patent 11348644 Memory device for performing dummy program operation and operating method thereof
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•••
Patent Inventor Names
Yi Song
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Jiahui Yuan
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Xiang Yang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11935593
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Patent Primary Examiner
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Vanthu T Nguyen
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CPC Code
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G11C 16/10
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G11C 16/28
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G11C 16/08
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G11C 16/0483
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