US Patent 11935619 Page buffer circuits of three-dimensional memory device

The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.