US Patent 11942409 High density low power interconnect using 3D die stacking

An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.