US Patent 11949871 Architecture flexible binary arithmetic coding system

In the subject architecture flexible binary arithmetic coding system, coding circuitry of an electronic device may receive video data that is to be coded (e.g., to be encoded or decoded) by binary arithmetic coding. The coding circuitry may also compute at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation (e.g., without performing a table look-up operation). The coding circuitry may perform binary arithmetic coding on the video data using the at least one of the LPS range or the MPS range. The computation of the LPS range and/or the MPS range using the multiplication operation may have a lower computational cost than using a table look-up operation.