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US Patent 11955412 Low stress asymmetric dual side module

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
September 6, 2022
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Date of Patent
April 9, 2024
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Patent Application Number
17929898
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Patent Citations
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US Patent 7569921 Semiconductor device and manufacturing method thereof
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US Patent 10418313 Electronic module comprising a plurality of encapsulation layers and a method for producing it
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US Patent 7438558 Three-dimensional stackable die configuration for an electronic circuit board
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US Patent 10242969 Semiconductor package comprising a transistor chip module and a driver chip module and a method for fabricating the same
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Patent Inventor Names
Stephen St. Germain
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Atapol Prajuckamol
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Chee Hiong Chew
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Yusheng Lin
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11955412
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Patent Primary Examiner
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Eugene Lee
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CPC Code
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H01L 25/0657
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H01L 23/49582
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H01L 23/49568
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H01L 23/4093
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H01L 23/367
0
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H01L 23/49575
0

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