US Patent 11960731 FIFO memory error condition detection

An apparatus can include first circuitry coupled to a FIFO memory. The first circuitry can provide a write pointer of the FIFO memory at a first rate. Second circuitry can be coupled to the FIFO memory. The second circuitry can provide a read pointer of the FIFO memory at a second rate that is different from the first rate. Third circuitry can be coupled to the first and second circuitries. The third circuitry can provide an indication of an error condition of the FIFO memory based on the write pointer and the read pointer.