US Patent 11966284 Fault-tolerant computer for reconfigurable hardware devices

A fault-tolerant computer system includes a plurality of processors configured to simultaneously execute identical sets of processor-executable instructions, each of the plurality of processors containing a processor core including one or more registers and a local memory, an arbiter configured to read each of the registers of the plurality of processors, detect incorrect register values, and overwrite the registers containing the incorrect register values with corrected register values, and a memory scrubber configured to read each address of the local memories of the plurality of processors, detect incorrect memory values, and overwrite addresses containing the incorrect memory values with corrected memory values. In various embodiments, the computer system may be implemented using one or more field programmable gate arrays (FPGAs).