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US Patent 11978664 Polishing interconnect structures in semiconductor devices
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Patent
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Date Filed
July 29, 2022
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Date of Patent
May 7, 2024
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Patent Application Number
17815975
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Patent Citations
US Patent 8563403 Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
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US Patent 10157987 Fin-based strap cell structure
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Patent Inventor Names
Li-Chieh Wu
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Fu-Kai Yang
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Pang-Sheng Chang
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Chun-Wei Hsu
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Kuo-Yi Chao
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Mei-Yun Wang
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Chao-Hsun Wang
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11978664
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Patent Primary Examiner
Karen Kusumakar
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CPC Code
H01L 21/76895
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H01L 21/76897
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H01L 21/76885
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H01L 23/5283
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H01L 21/3212
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H01L 21/31053
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H01L 23/53266
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H01L 23/5226
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H01L 21/76814
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H01L 21/7684
0
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