US Patent 11978737 Three-dimensional memory device and fabrication method thereof

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack, memory cells, a semiconductor layer, a contact structure, and gate line slit structures. The substrate includes a doped region. The layer stack is formed over the substrate. The memory cells are formed through the layer stack over the substrate. The semiconductor layer is formed on the doped region and a side portion of a channel layer that extends through the layer stack. The contact structure electrically contacts the doped region. A dielectric material is filled in the gate line slit structures. Air gaps are formed in the gate line slit structures by the dielectric material.