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US Patent 11979163 Oversampled phase lock loop in a read channel
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Patent
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Date Filed
October 3, 2022
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Date of Patent
May 7, 2024
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Patent Application Number
17958877
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Patent Citations
US Patent 7315598 Data recovery using data eye tracking
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US Patent 7733592 Methods for multi-channel data detection phase locked loop frequency error combination
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US Patent 7777980 Multi-channel data detection phase locked loop error combination logic
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US Patent 7974369 Phase detector for timing recovery loop
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US Patent 8054931 Systems and methods for improved timing recovery
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US Patent 8466713 Phase detection method and phase detector
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US Patent 8837656 Phase detection method and circuit
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US Patent 8964321 Iterative data storage read channel architecture having dropout mitigation
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US Patent 9214187 Cycle-slip resilient iterative data storage read channel architecture
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US Patent 10142089 Baud-rate clock data recovery with improved tracking performance
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•••
Patent Inventor Names
Derrick E. Burton
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Richard Galbraith
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Iouri Oboukhov
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11979163
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Patent Primary Examiner
James M Perez
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CPC Code
H03L 7/099
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H03L 7/0995
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H03L 7/0807
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H03L 7/091
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H03L 7/0998
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H03L 7/08
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H03L 7/10
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H03L 7/085
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H03L 7/087
0
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