US Patent 11980021 CMOS over array of 3-D DRAM device
Patent 11980021 was granted and assigned to Applied Materials on May, 2024 by the United States Patent and Trademark Office.
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US Patent 11980021 CMOS over array of 3-D DRAM device
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Patent abstract
Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.
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Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Fred Fishburn0
Sony Varghese0
Date of Patent
May 7, 2024
0Patent Application Number
178299390
Date Filed
June 1, 2022
0Patent Citations
Patent Primary Examiner
CPC Code
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