US Patent 11983477 Routing layer re-optimization in physical synthesis

To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.