US Patent 11989621 Tiling of cross-resonance gates for quantum circuits

Techniques regarding tiling a CR gate configuration to one or more lattices characterizing quantum circuit topologies are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tiling component that can generate a cross-resonance gate configuration that delineates a control qubit assignment and a target qubit assignment in conjunction with a frequency allocation onto a lattice characterizing a quantum circuit topology.