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US Patent 12001367 Multi-die integrated circuit with data processing engine array

Patent 12001367 was granted and assigned to Xilinx Inc on June, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Current Assignee
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Xilinx Inc
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Date Filed
May 18, 2023
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Date of Patent
June 4, 2024
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Patent Applicant
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Xilinx Inc
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Patent Application Number
18320147
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Patent Citations
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US Patent 7302625 Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration
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US Patent 7394288 Transferring data in a parallel processing environment
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US Patent 7477072 Circuit for and method of enabling partial reconfiguration of a device having programmable logic
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US Patent 7478357 Versatile bus interface macro for dynamically reconfigurable designs
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US Patent 7482836 High bandwidth reconfigurable on-chip network for reconfigurable systems
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US Patent 7509617 Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
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US Patent 7518396 Apparatus and method for reconfiguring a programmable logic device
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US Patent 7546572 Shared memory interface in a programmable logic device using partial reconfiguration
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US Patent 7619442 Versatile bus interface macro for dynamically reconfigurable designs
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US Patent 7640527 Method and apparatus for partial reconfiguration circuit design for a programmable device
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•••
Patent Inventor Names
Juan J. Noguera Serra
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Tim Tuan
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Sridhar Subramanian
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12001367
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Patent Primary Examiner
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Michael Sun
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