US Patent 12002525 Methods and apparatus for NAND flash memory

Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.