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US Patent 12002808 Dual dielectric pillar fork sheet device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
August 9, 2021
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Date of Patent
June 4, 2024
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Patent Application Number
17397242
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Patent Citations
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US Patent 9634091 Silicon and silicon germanium nanowire formation
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US Patent 9984936 Methods of forming an isolated nano-sheet transistor device and the resulting device
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US Patent 10332963 Uniformity tuning of variable-height features formed in trenches
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US Patent 10707303 Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts
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US Patent 10510620 Work function metal patterning for N-P space between active nanostructures
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US Patent 10957793 Method of forming target layer surrounding vertical nanostructure
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US Patent 7049652 Pillar cell flash memory technology
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US Patent 9614056 Methods of forming a tri-gate FinFET device
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Patent Inventor Names
Ruilong Xie
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Kangguo Cheng
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Julien Frougier
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Dimitri Houssameddine
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12002808
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Patent Primary Examiner
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Lex H Malsawma
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CPC Code
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H01L 29/42392
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H01L 29/66545
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H01L 29/66553
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H01L 29/66742
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H01L 29/78696
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H01L 29/0665
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H01L 21/823878
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H01L 21/823807
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H01L 21/0259
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H01L 27/092
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