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US Patent 12007895 Scalable system on a chip

Patent 12007895 was granted and assigned to Apple (company) on June, 2024 by the United States Patent and Trademark Office.

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 US Patent 12007895 Scalable system on a chip

Article

Patent abstract

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Infobox
Is a
Patent
Patent
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Patent Applicant
Apple (company)
Apple (company)
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Current Assignee
Apple (company)
Apple (company)
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120078950
Patent Inventor Names
Eran Tamari0
Gaurav Garg0
Harshavardhan Kaushikkar0
James Vash0
Jonathan M. Redshaw0
Lior Zimet0
Per H. Hammarlund0
Sagi Lahav0
Sergio Kolor0
Sergio V. Tota0
Shawn M. Fukami0
Steven R. Hutsell0
Date of Patent
June 11, 2024
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Patent Application Number
178213050
Date Filed
August 22, 2022
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Patent Citations
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US Patent 7098541 Interconnect method for directly connected stacked integrated circuits
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US Patent 7171534 System and method for multi-modal memory controller system operation
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US Patent 7340548 On-chip bus
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US Patent 7480770 Semi-blocking deterministic directory coherence
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US Patent 7580309 Memory refresh method and system
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US Patent 7721035 Multiprocessor system, processor and interrupt control method
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US Patent 8190820 Optimizing concurrent accesses in a directory-based coherency protocol
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US Patent 8190855 Coupling data for interrupt processing in a parallel processing environment
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US Patent 8260996 Interrupt optimization for multiprocessors
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US Patent 8291245 Method, apparatus and system for reducing power consumption based on storage device data migration
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US Patent 8321650 Alignment-unit-based virtual formatting methods and devices employing the methods
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US Patent 8327187 Low-overhead operating systems
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US Patent 8458386 Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements
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US Patent 8670261 Stub minimization using duplicate sets of signal terminals
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US Patent 8732496 Method and apparatus to support a self-refreshing display device coupled to a graphics controller
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US Patent 8751864 Controlling memory redundancy in a system
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US Patent 8786069 Reconfigurable pop
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US Patent 8874855 Directory-based coherence caching
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US Patent 8959270 Interrupt distribution scheme
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US Patent 9009368 Interrupt latency performance counters
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US Patent 9029234 Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking
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US Patent 9170946 Directory cache supporting non-atomic input/output operations
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US Patent 9201608 Memory controller mapping on-the-fly
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US Patent 9244874 Selectively transparent bridge for peripheral component interconnect express bus systems
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US Patent 9348762 Technique for accessing content-addressable memory
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US Patent 9355034 Removal and optimization of coherence acknowledgement responses in an interconnect
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US Patent 9405303 Power stealing for a wireless-enabled thermostat
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US Patent 9424191 Scalable coherence for multi-core processors
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US Patent 9442869 Programmable interrupt routing in multiprocessor devices
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US Patent 9620181 Adaptive granularity row-buffer cache
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US Patent 9678564 Multiprocessor system with interrupt distributor
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US Patent 9747225 Interrupt controller
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US Patent 10153006 Stacked semiconductor device and control method for the same
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US Patent 10403333 Memory controller with flexible address decoding
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US Patent 10523585 System on a chip comprising multiple compute sub-systems
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US Patent 10534719 Memory system for a data processing network
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US Patent 10585826 Using processor types for processing interrupts in a computing device
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US Patent 10673439 Adaptive integrated programmable device platform
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US Patent 10733350 On-chip and system-area multi-processor interconnection networks in advanced processes for maximizing performance minimizing cost and energy
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US Patent 11016810 Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture
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US Patent 11061850 Multiple transaction data flow control unit for high-speed interconnect
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US Patent 11327786 Distributing interrupt request to be handled by target virtual processor
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US Patent 11544193 Scalable cache coherency protocol
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US Patent 6976115 Peer-to-peer bus segment bridging
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Patent Primary Examiner
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Scott C Sun
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