US Patent 12009262 Semiconductor device having planar transistor and FinFET

A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.