Patent attributes
A computer system implements a memory unit, which includes first DRAM devices, second DRAM devices, a first memory controller, and a second memory controller. Each of the first DRAM devices have a first individual memory capacity and each of the second DRAM devices have a second individual memory capacity. The first memory controller is in signal communication with the first DRAM devices and the second memory controller is in signal communication with the second DRAM devices. Each of the first DRAM devices and the second DRAM devices are selectively operable as one of an active DRAM device to stare application data or a spare DRAM device reserved to receive the application data from the active DRAM devices to dynamically over-provision a total memory defined by a sum of the first and second individual memory capacities.
