US Patent 12020752 Discharge circuits for erasing NAND flash memory

The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.