Patent attributes
A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.
