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US Patent 12022659 Three-dimensional memory device and method

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Date Filed
July 27, 2022
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Date of Patent
June 25, 2024
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Patent Application Number
17874844
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Patent Citations
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US Patent 9240420 3D non-volatile storage with wide band gap transistor decoder
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US Patent 9997631 Methods for reducing contact resistance in semiconductors manufacturing process
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US Patent 10043819 Method for manufacturing 3D NAND memory using gate replacement, and resulting structures
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US Patent 10256247 Three-dimensional memory device with silicided word lines, air gap layers and discrete charge storage elements, and method of making thereof
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US Patent 10490571 Semiconductor device having ferroelectric layer and method of manufacturing the same
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US Patent 10515981 Multilevel semiconductor device and structure with memory
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US Patent 10553604 Through array contact structure of three-dimensional memory device
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US Patent 10720441 Three-dimensional semiconductor memory device
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US Patent 10777566 3D array arranged for memory and in-memory sum-of-products operations
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US Patent 10868042 Ferroelectric memory device containing word lines and pass gates and method of forming the same
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•••
Patent Inventor Names
Sheng-Chen Wang
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Meng-Han Lin
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Han-Jong Chia
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Feng-Cheng Yang
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Chung-Te Lin
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Yu-Ming Lin
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12022659
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Patent Primary Examiner
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Matthew E Warren
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CPC Code
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G11C 11/2255
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H01L 29/78391
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H01L 29/66833
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H01L 29/66787
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H01L 29/66666
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H01L 23/5226
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