US Patent 12026605 FeFET unit cells for neuromorphic computing

A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.