Patent attributes
A memory device that may include a primary PCB that is configured to support one or more SSD units and one or more volatile memory units; a secondary PCB that is configured to mechanically support multiple supercapacitors; wherein the secondary PCB comprises an aperture and an array of heat different reduction elements configured to reduce temperature differences between different parts of the secondary PCB; a board to board connector for electrically coupling at least one electrical conductor of the primary PCB to at least one electrical conductor of the secondary PCB; a mechanical interface that has a base, a top section and a threaded hole that passes through the base and the top section; wherein the base is wider than the top section; wherein the top section is shaped and sized to enter the aperture of the secondary PCB; wherein the base is configured to support the secondary PCB when the top section enters the aperture. The height of the base, a height of the board to board connector, and a width of the secondary PCB may be smaller than a millimeter.