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US Patent 12079555 Automated circuit generation
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Patent
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Date Filed
May 8, 2023
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Date of Patent
September 3, 2024
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Patent Application Number
18314004
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Patent Citations
US Patent 8001494 Table-based DFM for accurate post-layout analysis
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US Patent 10285276 Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell
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US Patent 10289793 System and method to generate schematics from layout-fabrics with a common cross-fabric model
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US Patent 10558780 Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design
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US Patent 10671700 Systems and methods for obfuscating a circuit design
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US Patent 10699051 Method and system for performing cross-validation for model-based layout recommendations
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US Patent 10770160 Programmable resistive memory formed by bit slices from a standard cell library
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US Patent 10783292 Automated analog layout
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US Patent 10783296 Matched net and device analysis based on parasitics
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US Patent 10796059 Integrated circuit layout generation method and system
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•••
Patent Inventor Names
Muhammed Abid Hussain
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Karen Mason
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Richard Philpott
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John Mason
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Calum MacRae
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Jim LoCascio
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12079555
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Patent Primary Examiner
Phallaka Kik
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CPC Code
G06F 30/367
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G06F 30/398
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G06F 30/327
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G06F 30/38
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G06F 30/31
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G06F 30/373
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G06F 2111/12
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G06F 30/347
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G06F 30/392
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