US Patent 12080704 Memory cell array and method of operating same

A memory circuit includes a first and a second bit line, a first and a second inverter, a P-type pass gate transistor, a pre-charge circuit, a first transmission gate and a sense amplifier. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to at least the first bit line or the second bit line, and configured to charge at least the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level. The first transmission gate is coupled to the first bit line, and configured to receive a first and a second control signal. The sense amplifier is coupled to the first bit line by the first transmission gate.