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US Patent 12088691 Clock and data recovery circuit, method and apparatus
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Patent
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Date Filed
March 24, 2021
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Date of Patent
September 10, 2024
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Patent Application Number
17906984
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Patent Citations
US Patent 9960902 Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit
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US Patent 9705708 Integrated circuit with continuously adaptive equalization circuitry
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US Patent 10181941 Sampling phase adjustment device and adjusting method thereof
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US Patent 9350572 Apparatus for clock and data recovery
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US Patent 9455848 DFE-skewed CDR circuit
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Patent Inventor Names
Xinjian Chen
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Yuanjun Liang
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12088691
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Patent Primary Examiner
Aristocratis Fotakis
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CPC Code
H04L 7/0334
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H04L 25/03885
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H04L 7/0058
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H04L 7/033
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H04L 7/0062
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H04L 7/0087
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H03L 7/091
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H03L 7/0807
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H03L 7/085
0
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