Patent attributes
An arithmetic device includes N product-sum-operation circuits, a control circuit, and an output circuit. Each product-sum-operation circuit outputs intermediate signals obtained by binarizing a product-sum-operation value obtained by product-sum-operation of M input values of M input signals and M weight values. The control circuit inverts positive/negative of each M weight value at determining-timing when a given time elapses from input timing. Based on a delay time from the determination-timing to logic finalization of the intermediate signal for each N product-sum-operation circuit, the output circuit outputs an output signal representing a winner-product-sum-operation circuit for which the product-sum-operation value having a sign and the largest absolute value is calculated. Each N product-sum-operation circuit starts the product-sum-operation from the input-timing and the determination-timing, and outputs an intermediate signal for which a propagation-delay-time from starting of the product-sum-operation to inversion of the logic corresponds to the absolute value of the product-sum-operation value.
