Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Mark McDermott0
Aseem Sayal0
Paras Ajay0
Shrawan Singhal0
Sidlgata V. Sreenivasan0
Jaydeep Kulkarni0
Ovadia Abed0
Date of Patent
September 17, 2024
0Patent Application Number
180810470
Date Filed
December 14, 2022
0Patent Citations
Patent Primary Examiner
CPC Code
Patent abstract
A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.