US Patent 12105548 Improving power supply rejection ratio across load and supply variances

Described embodiments include a circuit for reducing output voltage noise in a voltage regulator includes an amplifier having first and second amplifier inputs, a compensation terminal and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the compensation terminal coupled to an output terminal. A buffer amplifier has a buffer input and a buffer output, and the buffer input is coupled to the amplifier output. A first transistor is coupled between a supply voltage terminal and the output terminal, and has a first control terminal that is coupled to the buffer output. A boost current injection circuit has a boost input and a boost output, and the boost input is coupled to the supply voltage terminal. A second transistor is coupled between the boost output and the compensation terminal, and has a second control terminal.