US Patent 12105589 Parity-based error management for a processing system
Patent 12105589 was granted and assigned to Micron Technology on October, 2024 by the United States Patent and Trademark Office.
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US Patent 12105589 Parity-based error management for a processing system
Article
Patent abstract
Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.
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Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Ameen D. Akel0
Helena Caminal0
Sean S. Eilert0
Date of Patent
October 1, 2024
0Patent Application Number
176522310
Date Filed
February 23, 2022
0Patent Citations
Patent Primary Examiner
CPC Code
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