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US Patent 12106034 Rule check violation prediction systems and methods

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
August 10, 2023
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Date of Patent
October 1, 2024
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Patent Application Number
18447455
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Patent Citations
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US Patent 7861203 Method and system for model-based routing of an integrated circuit
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US Patent 8510689 Method and system for implementing context simulation
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US Patent 8713484 Aware manufacturing of integrated circuits
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US Patent 8716869 Cell array and density features with decoupling capacitors
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US Patent 8719746 Reduction of metal fill insertion time in integrated circuit design process
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US Patent 8806414 Method and system for layout parasitic estimation
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US Patent 8839177 Method and system allowing for semiconductor design rule optimization
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US Patent 9690898 Generative learning for realistic and ground rule clean hot spot synthesis
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US Patent 9792397 System and method for designing system on chip (SoC) circuits through artificial intelligence and reinforcement learning
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US Patent 10089433 Method for triple-patterning friendly placement
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•••
Patent Inventor Names
Szu-Ju Huang
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Yin-An Chen
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Henry Lin
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Amos Hong
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Yi-Lin Chuang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12106034
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Patent Primary Examiner
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Paul Dinh
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CPC Code
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G06N 20/00
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G06F 30/27
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G06F 30/394
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G06F 30/392
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G06F 30/327
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G06F 30/398
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