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US Patent 12118328 In-memory bit-serial addition system

Patent 12118328 was granted and assigned to Purdue Research Foundation on October, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Current Assignee
Purdue Research Foundation
Purdue Research Foundation
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Date Filed
June 3, 2023
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Date of Patent
October 15, 2024
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Patent Applicant
Purdue Research Foundation
Purdue Research Foundation
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Patent Application Number
18205528
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Patent Citations
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US Patent 11043259 System and method for in-memory compute
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Patent Inventor Names
Kaushik Roy
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Akhilesh Jaiswal
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Mustafa Ali
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12118328
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Patent Primary Examiner
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Andrew Caldwell
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CPC Code
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G06F 17/16
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G06F 2207/4822
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G06F 7/74
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G06F 7/4912
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