Patent attributes
An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.
