Patent attributes
An apparatus for synchronous Ethernet comprises a processor, a field programmable gate array, a synchronizer, a physical layer implementor and a media accessing controller, wherein, the processor transmits a control data through a first transmission interface; the field programmable gate array receives the control data, generates a control instruction in accordance with the control data and transmits the control instruction through a second transmission interface; the synchronizer receives the control instruction and generates a synchronous clock in accordance with the control instruction; and each of the physical layer implementor and the media accessing controller receives and works in accordance with the synchronous clock and media accessing control protocol.
