US Patent 12137169 Low latency post-quantum signature verification for fast secure-boot
Patent 12137169 was granted and assigned to Intel on November, 2024 by the United States Patent and Trademark Office.
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US Patent 12137169 Low latency post-quantum signature verification for fast secure-boot
Article
Patent abstract
In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
Infobox
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Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Andrew H. Reinders0
Manoj Sastry0
Rafael Misoczki0
Raghavan Kumar0
Santosh Ghosh0
Sanu Mathew0
Vikram Suresh0
Date of Patent
November 5, 2024
0Patent Application Number
178549110
Date Filed
June 30, 2022
0Patent Citations
Patent Primary Examiner
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