US Patent 6838721 Integrated circuit with a transitor over an interconnect layer

An integrated circuit (101) includes electrical circuitry (105) formed on a substrate (103). An interconnect layer (109, 117) is formed over the electrical circuitry (105). In one example, a plurality of magneto-resistive random access memory cells (MRAM) (161, 171) is implemented above the interconnect layer. Each of the MRAM cells comprises a magneto-resistive tunnel junction (MTJ) storage element. A transistor (130) is formed-over the interconnect layer (109, 117). In one embodiment, the transistor is implemented as a thin film transistor (TFT). In one embodiment the transistor is a select transistor and may be coupled to one or more of the MTJ storage elements. Access circuitry (203, 205, 207, 209) is formed on the substrate (103) under the plurality of MRAM cells (161, 171).