US Patent 6856950 Abstract verification environment
Patent 6856950 was granted and assigned to Silicon Graphics on February, 2005 by the United States Patent and Trademark Office.
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Patent abstract
A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.
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Patent Inventor Names
Dennis Abts0
Michael Roberts0
Date of Patent
February 15, 2005
0Patent Application Number
094187060
Date Filed
October 15, 1999
0Patent Primary Examiner
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US Patent 6856950 Abstract verification environment
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