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US Patent 6873926 Methods and apparatus for testing a clock signal

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Patent
Patent
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Patent attributes

Patent Applicant
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
68739260
Patent Inventor Names
Wael Diab0
Date of Patent
March 29, 2005
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Patent Application Number
097944530
Date Filed
February 27, 2001
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Patent Citations Received
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US Patent 12072376 Die-to-die connectivity monitoring
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US Patent 12013800 Die-to-die and chip-to-chip connectivity monitoring
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US Patent 12123908 Loopback testing of integrated circuits
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US Patent 12092684 Integrated circuit workload, temperature, and/or sub-threshold leakage sensor
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US Patent 11841395 Integrated circuit margin measurement and failure prediction device
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US Patent 11929131 Memory device degradation monitoring
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Patent Primary Examiner
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Michael Nghiem
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Patent abstract

Techniques test a clock signal by comparing different portions of that clock signal to each other. Such techniques enable the detection of a clock signal having anomalies such as missing pulses or occasional delayed pulses. In one arrangement, a data communications device has a clock signal generator, processing circuitry and a test circuit, both of which are coupled to the clock signal generator. The clock signal generator provides a clock signal. The processing circuitry uses the clock signal to receive data elements on a set of input ports, and to transmit the data elements on a set of output ports. The test circuit includes a node that receives the clock signal, a comparison circuit that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal, and an output circuit that provides a result signal based on the comparison signal.

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