Patent attributes
According to one exemplary embodiment, an ESD bus clamp in an integrated circuit comprises an inverter having an input and an output. The ESD bus clamp further comprises a bipolar transistor having a base, an emitter, and a collector, where the base is connected to the output of the inverter, the emitter is connected to a ground of the integrated circuit, and the collector is connected to a power bus of the integrated circuit. The bipolar transistor, for example, may be an NPN bipolar transistor and may begin shunting current to the ground when an ESD discharge causes a voltage level on the power bus to increase by approximately 1.0 volt. According to this exemplary embodiment, the ESD bus clamp further comprises a resistor coupling the input of the inverter to the power bus. The ESD bus clamp further comprises a capacitor coupling the input of the inverter to ground.
