US Patent 6930003 Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method of manufacturing a semiconductor device including the steps of: forming a gate insulation layer above a semiconductor layer; forming a first conductive layer and a stopper layer having a predetermined pattern above the gate insulation layer; forming a first insulation layer and a second conductive layer over the entire surface of the memory region; forming a first side-wall conductive layer on each of both side surfaces of the first conductive layer, and on the semiconductor layer with the first insulation layer interposed, by anisotropic etching of that second conductive layer; forming a third conductive layer over the entire surface of the memory region; forming a second side-wall conductive layer on each of both side surfaces of the first conductive layer, and on the semiconductor layer with the second insulation layer interposed, by anisotropic etching of that third conductive layer; and forming control gates by isotropic etching of the first and second side-wall conductive layers.