Patent 6930522 was granted and assigned to Intel on August, 2005 by the United States Patent and Trademark Office.
A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.