Patent attributes
A serial read-only memory (SROM) device having an address range includes a memory array, an address clock pin for receiving an address clock signal, which starts an address cycle, a data clock pin for receiving a data clock signal, which starts a data cycle, a chip select/cascade (CS/CAS) pin for receiving a first control signal during the address cycle and for receiving a second control signal during the data cycle, a first data pin for receiving an address during the address cycle and for sending data during the data cycle, and a second data pin for receiving external data, the second data pin being connectable to the first data pin through a cascading data path defined therebetween, wherein the external data received at the second data pin may be transmitted to the first data pin when the cascading data path is connected.
