Patent attributes
First dummy memory cells that store first logic and second dummy memory cells that store second logic that is reverse of the first logic are connected to a dummy word line. The first and second dummy memory cells are connected to a dummy bit line. A dummy sense amplifier activates a sense amplifier start signal for a real sense amplifier when the voltage of the dummy bit line varies. When real memory cells are read, the speed at which the first dummy memory cells cause the level of the dummy bit line to vary to the first logic level decreases due to the second logic level stored in the second dummy memory cells. The lower the threshold voltages of transistors, the more obvious this tendency becomes. Thus, the operation start timing of the sense amplifier can be optimally set even if a fabricating condition of a semiconductor memory varies.
