Patent attributes
In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
