US Patent 6965539 Write path scheme in synchronous DRAM

A write path scheme in a synchronous DRAM having: a data converter unit to convert serial input data to parallel output data, a multiplexer to output data from the data converter unit depending on a first mode selection signal and a second mode selection signal, and a data input/output sense amplifier having a plurality of sense amplifiers to separately operate the plurality of sense amplifiers depending on the first mode selection signal and the second mode selection signal to sense data from the multiplexer and then load the data on a global input/output line. Also included is a write driver to load data from the global input/output line on a local input/output line.