Patent attributes
A NAND flash memory device is provided. The memory device includes M input/output pins for inputting and outputting M-bit data (M is any natural number), first and second input buffer circuits, an address register, a command register, and a data input register. The first and second input buffer circuits receive N least significant bits (N is any natural number) and N most significant bits, respectively, of the M-bit data inputted via the input/output pins. The address register receives as an address an output of the first input buffer circuit in response to address load signals. The command register receives as a command an output of the first address buffer circuit in response to the command load signal. The data input register simultaneously receives outputs of the first and second input buffer circuits in response to the data load signal, as data to be programmed. The M-bit data latched in the data input register is loaded on the sense and latch block via a data bus. According to these configurations of the NAND flash memory device, at each of modes of operation where a command, an address, and data are serially received, the data is inputted and outputted through all of the M input/output pins, while each of the command and the address is inputted through N least significant bit input/output pins.
